Arithmetic & Logic Unit (ALU)

The ALU subsystem actually contains two units with independent X
and Y inputs for both.

## ALU1

This is made up of several sections:

In addition there is

The adder and logic units are inherently dyadic. Monadic operations are implemented from these:

For the BTST/BCLR/BSET/BCHG instructions the required bit masks are generated locally using a 4:16 decoder. For these instructions the status flag calculation needs to know the value of the targeted bit before the instruction execution. Whilst the logic unit could do this it will be being used to actually carry out the instruction. There is therefore extra logic for calculating the value of the targeted bit.

For the ALU type instructions the X and Y inputs will usually be driven by the RA and RB buses from the General Purpose Registers. It can generate small constants locally if required (0, ±1, ±2). For load/store instructions ALU1 may be used for address calculations.

## ADDER2

ADDER2 only implements just addition/subtraction. It is
implemented using two 8 bit adder/subtractor boards.

For most instructions ADDER2 is used for incrementing the PC whilst ALU1 carries out the operation of the instruction. It was originally tightly coupled with the PC and not available for other calculations. It moved to the ALU to be able to takle part in other calculations. (It gets involved in the complex iterative instructions of Multiply, Divide and Square root which are described here.) This move was probbaly a mistake, I should have just added an extra adder.

- a 16 bit adder made from two 8 bit adder/subtractor boards. This does addition and subtraction
- a 16 bit logic unit made from two 8 bit logic boards. This does AND, OR and XOR operations
- a 16 bit left shifter
- a 16 bit right shifter

In addition there is

- bit test logic (determines if selected bit of X input is set or clear)
- status flag calculation

The adder and logic units are inherently dyadic. Monadic operations are implemented from these:

-X = 0 - X

~X = 0xFFFF ^ X

~X = 0xFFFF ^ X

For the BTST/BCLR/BSET/BCHG instructions the required bit masks are generated locally using a 4:16 decoder. For these instructions the status flag calculation needs to know the value of the targeted bit before the instruction execution. Whilst the logic unit could do this it will be being used to actually carry out the instruction. There is therefore extra logic for calculating the value of the targeted bit.

For the ALU type instructions the X and Y inputs will usually be driven by the RA and RB buses from the General Purpose Registers. It can generate small constants locally if required (0, ±1, ±2). For load/store instructions ALU1 may be used for address calculations.

For most instructions ADDER2 is used for incrementing the PC whilst ALU1 carries out the operation of the instruction. It was originally tightly coupled with the PC and not available for other calculations. It moved to the ALU to be able to takle part in other calculations. (It gets involved in the complex iterative instructions of Multiply, Divide and Square root which are described here.) This move was probbaly a mistake, I should have just added an extra adder.

© 2014-2016 James Newman.