This zip file contains an assembler and simulator for the Megaprocessor with some example programs.
Mega_processor_sw
You're welcome to play !

The instruction set is defined in this document.
The user guide for the simulator is this document.
And the user guide for the assembler is this document.

The hex files that the assembler creates can not only run in the simulator, but can also be downloaded to the Megaprocessor itself. So if you  ever come to visit remember to bring them with you.

Here is an overview of the instruction set.

Definitions for the main table:

RA	Destination. Any of registers R0, R1, R2, R3
RB	Source. Any of registers R0, R1, R2, R3 (possibly with exception of RA, see notes)
RC	Destination. May be either R0 or R1
RI	Index. May be either R2 or R3
sz	Size. May be B for byte or W for word
wt	Weight. Used to specify the calculation of a weight (count of ones) value.

Instruction	Notes
ABS      RA
ADD      RA,RB	RB may equal RA
ADDI     SP, #data	data is 8 bit signed value
ADDQ     RA, #small	The small value may be 1, 2, -1, or -2. This instruction is encoded as a single byte.
ADDX     R0, R1
AND      RA, RB	RB may not equal RA
ANDI     PS, #data	data is 8 bits
ASL[.wt] RA, descriptor ASR[.wt] RA, descriptor	Arithmetic shift. See notes on shift instructions below.
Bcc      address	Conditional branch. The target is stored as a signed 8 bit displacement, -128...127. There are 16 possibilities: BCC:  C clear BCS:  C set BNE: Z clear (not equal) BEQ: Z set (equal) BVC: V clear BVS: V set BPL: N clear (plus) BMI: N set (minus) BGE: BLT: BGT: Use for 2s complement numbers BLE: Use for 2s complement numbers BUC: U clear BUS: U set BHI: Branch Higher. Similar to BGT but for unsigned numbers BLS: Branch on Lower or Same. Similar to BLE but for unsigned numbers
BCHG      RA, descriptor	Invert specified bit in destination register. See notes on BIT instructions below
BCLR      RA, descriptor	Clear specified bit in destination register. See notes on BIT instructions below
BSET      RA, descriptor	Set specified bit in destination register. See notes on BIT instructions below
CLR       RA	Alias for XOR RA, RA
CMP       RA, RB	RB may not equal RA
DEC       RA	Alias for ADDQ RA, #-1
DIVS DIVU	This calculates R0/R1. R0 and R1 are left unchanged. R2 holds the quotient. R3 holds the remainder. There are two ways of defining signed division, both have validity. Both are implemented, controlled by the D bit of the PS register. The difference lies in whether or not negative remainders are allowed. D = 0 D = 1 13/3 Q = 4, R = 1 Q = 4, R = 1 13/-3 Q = -4, R = 1 Q = -4, R = 1 -13/3 Q = -4, R = -1 Q = -5, R = 2 -13/-3 Q = 4, R = -1 Q = 5, R = 2 Divide by zero is trapped and causes vector #2 to be taken.
INC       RA	Alias for ADDQ RA, #1
INV       RA	Invert all bits
JMP       (R0) JMP       address	Jump to specified location.
JSR       (R0) JSR        address	Jump to subroutine, pushes return address on stack
LD.sz      RA, address LD.sz      RC, (RI) LD.sz      RC, (RI++) LD.sz      RA, (SP + m) LD.sz      RA, #immediate	Bytes are zero extended on loading to fill the 16 bit destination register. The m value used for stack relative addressing is 8 bit unsigned.
LSL[.wt]   RA, descriptor LSR[.wt]   RA, descriptor	Logical shift. See notes on shift instructions below.
MOVE       RA, RB MOVE       R0, SP MOVE       SP, R0	RB may not equal RA
MULS MULU	This calculates R0*R1 to create a 32 bit result. The least significant 16 bits of the result are stored in R2, the most significant 16 bits are stored in R3. If it is a signed operation then R0 will hold the value of an internal calculation. If it is an unsigned operation R0 will be unchanged. R1 is always left unchanged.
NEG        RA
NEGX       R0
NOP
OR         RA, RB	RB may not equal RA
ORI        PS, # data	data is 8 bits
POP        RA POP        PS
PUSH       RA PUSH       PS
RET	Return from subroutine
RETI	Return from interrupt/exception
ROL[.wt]   RA, descriptor ROR[.wt]   RA, descriptor	Rotate. See notes on shift instructions below.
ROXL[.wt]  RA, descriptor ROXR[.wt]  RA, descriptor	Rotate extended with X bit. See notes on shift instructions below.
SQRT	This calculates the square root of R1. The result, rounded down, is put into R0. R1 holds the remainder. R2 is unchanged. R3 will be set to zero.
ST.sz      address, RA ST.sz      (RI), RC ST.sz      (RI++), RC ST.sz      (SP + m), RA	The m value used for stack relative addressing is 8 bit unsigned.
SUB        RA, RB	RB may not equal RA
SUBX       R0, R1
SXT        RA	Sign extend LS byte of register to fill the register
TEST       RA	Set status bits Z, N according to register
TRAP	Pushes PS and return address and then takes vector #3.
XOR        RA, RB	RB may equal RA

Bit Instruction Descriptors:
The descriptor specifies the target bit and may be either a 4 bit immediate value or a general purpose register (R0..R3). If a register is specified then only the least significant 4 bits are used. For example:
BSET        R0, #3
BCLR        R1, R2

Shift Instruction Descriptors:
The descriptor specifiers the shift to apply and is a 15 bit signed value ranging -16..15. It may be either a 5 bit signed immediate value or a general purpose register (R0..R3). If a register is specified then only the least significant 5 bits are used. For example:

LSL         R0, #3
ASR         R1, R2

If the descriptor is a register then the instruction may be qualified with ".wt" in which case a weight value is calculated. The shift is executed as specified and the number of times a 1 valued bit is shifted out of the least significant register position is counted. At the end of the shift operation this count is stored in the destination register rather than the result of the shift. For example:
ASR.wt      R1, R2